The present application relates to a semiconductor structure and a method for fabricating the same. More particularly, the present application relates to slurry compositions and a method for planarizing a Group III arsenide material, which can be used, for instance, in fabrication of semiconductor structures, such as, n-type MOSFETs (NFET) devices.
As the density of semiconductor integrated circuits increases and the corresponding size of circuit elements decreases, one of the key strategies to increase performance at lower operating voltages is to increase carrier mobility in the channel region. By way of an example, the carrier mobility in the channel region may be enhanced, for instance, by employing a non-silicon, high mobility charge carrier material such as, for example, germanium or a III-V compound semiconductor material, in the fabrication of the channel region. For instance, high electron mobility materials, such as, for example, III-V semiconductor materials are utilized for fabricating n-type MOSFET (PFET) devices. These III-V semiconductor materials which may be, or include, materials such as, indium phosphide (InP), gallium arsenide (GaAs), InGaAs, InAs, GaSb, and InSb exhibit outstanding electron transport properties with bulk mobility of 104 cm2 V−1 s−1 or higher.
The fabrication of semiconductor material, for example, a Group III arsenide material, on a semiconductor substrate, such as, a silicon wafer, disadvantageously, leads to several issues such as, for instance, defect densities, owing to a high lattice mismatch of the Group III arsenide material and the silicon wafer. For instance, the differences in lattice constants of the III-V compound semiconductor material (e.g., gallium arsenide) and the silicon wafer (which, in one example, may have (100) crystallographic orientation) results in a lattice mismatch of 4% for the gallium arsenide material on the silicon wafer. Disadvantageously, such lattice mismatch could result in threading dislocations during the epitaxial growth of the gallium arsenide material over the silicon wafer. In one example, the typical defect densities for the gallium arsenide material grown on the silicon wafer are of the order of 108/cm2. The extremely high number of defect densities could degrade the electron mobility and may enhance junction leakage resulting in poor transistor performance. Aspect ratio trapping is one way to overcome the lattice mismatch which, for instance, includes trapping threading dislocations of the gallium arsenide material along the sidewalls of the dielectric layer disposed over the semiconductor substrate, such as, for instance, a silicon substrate. This results in a portion of the gallium arsenide material that extends above the dielectric layer, and is subsequently planarized using a chemical mechanical planarization (CMP) processes.
Enhancements in CMP processing techniques and slurry compositions employed therein continue to be desired for enhanced performance, while minimizing surface and sub-surface damage.